ARM-specific architecture state of a thread. More...
ARM-specific architecture state of a thread.
Architecture code-private part of thread record.
This structure holds additional state needed by the ARM Cortex M CPUs to properly store/restore thread state.
As of now the floating point usage information is stored here. This is provided only if FPU is available and activated.
This structure holds the CPU-specific part of thread state. It can be empty if architecture does not need any specific information saved in the CPU state.